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Application Note 9846
? Examine state transitions
For subsequent transitions into standby states, leave the
main ATX outputs enabled (SW1 on); the circuit will
automatically turn them off when entering a standby state. To
enter a standby state, turn on the respective switch. The ‘S3’
LED will light up to indicate S3 standby state, while S5 state
will illuminate both ‘S3’ and ‘S5’ LEDs. However, the
HIP6501A will ignore any illegal transition requests, such as
from S3 state to S5 state or vice versa, as shown in Figure 1.
FULL ACTIVE
S0
S1, S2
Configuring Sleep State Support
Sleep state support on the 3.3V DUAL and 5V DUAL outputs is
user-configurable through jumpers JP1 and JP2 (consult
data sheet for sleep support details, [5]). The configuration
can be changed prior to 5VSB application, during active
state operation, as well as during chip shutdown (PB1
pressed). During sleep states, the configuration is latched in
and any changes in the EN3VDL and EN5VDL pins’ logic
status are ignored.
HIP6501AEVAL1 Reference Design
General
The HIP6501AEVAL1 is built on 2-ounce, 4-layer, printed
circuit board (see last three pages of this application note for
ACTIVE
IDLE
layout plots). Most of the components specific to the
STATES
S3
STR
SLEEP
STATES
S4, S5
evaluation board alone, which are not needed in a real
computer application, are placed on the bottom side of the
board. Assuming the input supplies and the controlled output
planes have their own on-board filtering (capacitors), the
only components required to implement this ACPI 3-voltage
controller/regulator solution are contained within the white
rectangle surrounding the HIP6501A on the top side of the
LEGEND:
STR - SUSPEND TO RAM
STD, SOFT-OFF
board. All the additional circuitry contained on board has the
role of duplicating the computer environment the chip would
STD - SUSPEND TO DISK
- LEGAL TRANSITION
- ILLEGAL TRANSITION (REQUEST IGNORED BY THE HIP6501A)
FIGURE 1. HIP6501A LEGAL/ILLEGAL STATE TRANSITIONS
Fault Handling
In case of a FAULT condition (output under-voltage)
occurring while in active state (such as a suddenly shorted
output), the FAULT/SEL pin assesses a logic ‘high’, shutting
down the ATX supply’s main outputs. To recover from such a
shutdown, press the ‘SHUTDOWN/CLEAR FAULT’ button
(PB1). Depressing PB1 will initiate a soft-start sequence,
thus clearing the FAULT, and enabling the main ATX outputs.
If jumper JP3 (FAULT LATCH) is removed, the FAULT output
will not latch the circuit. The circuit appears to latch off
because the FAULT signal shuts down the ATX supply,
cutting off the input supply to the faulting output, and thus
keeping it from ever recovering from the fault condition.
However, it is not recommended to test the circuit against
output under-voltages (output short-circuits) with JP3
removed . Due to the very slow response of the ATX supply
in response to a shutdown request, the external N/P-MOS
switches (Q3A, Q3B, and Q4) in use at the time of testing
will usually fail as a result of sustained over-current through
the drain-source junction and bond wires. The FAULT latch
circuit acts on the SS pin directly, shutting down the IC
quickly. To protect the external switches it is recommended
that JP3 is shunted throughout the operation of the board.
operate in. Since this additional circuitry would clutter and
detract from the readability of the schematic, most of it was
grouped in two blocks, named “SIGNAL CONDITIONING”
and “FAULT LATCH”.
The board also contains a serpentine resistor which
occupies about 1/3 of both top and bottom sides of the
board. The ATX supply requires some minimum loading on
the +5V output in order to stay active; lack of this minimum
loading causes the ATX to shut down all its outputs, except
+5VSB. This minimum load is specified as 1A, but most
supplies will stay active with as little as 400-500mA. The
embedded resistor should draw a current of about 1A
(typical). If the current draw is insufficient to keep the power
supply active, try reducing the value of the embedded
resistor. Shorting out the W1 footprint, on the back side of
the board, effectively shorts out 1/4 of the resistive trace,
increasing the current draw by 30%. Similarly, shorting out
W2 reduces the trace by 50%, thus doubling the current
draw from the +5V output. If either W1 or W2 are shorted, it
is advised that active state operation be reduced as to avoid
severe overheating of the board (in case the 5V current draw
exceeds 1A). For most, if not all cases, neither W1 nor W2
need be shorted.
Design Envelope
Although different computer systems might have different
requirements, the HIP6501AEVAL1 was designed to meet
the maximum output loading described in Table 1. Note the
fact that the addition of all the sleep state output currents
exceeds the ATX 5VSB output capability (725mA). Real-life
sleep state current requirement on each of the outputs could
2
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